Use of floating point on typical mailserver
Jeff A. Earickson
jaearick at colby.edu
Thu Feb 1 21:03:10 CET 2007
On Thu, 1 Feb 2007, Greg Matthews wrote:
> Date: Thu, 01 Feb 2007 11:20:20 +0000
> From: Greg Matthews <gmatt at nerc.ac.uk>
> Reply-To: MailScanner discussion <mailscanner at lists.mailscanner.info>
> To: MailScanner discussion <mailscanner at lists.mailscanner.info>
> Subject: Use of floating point on typical mailserver
>
> I'm considering evaluating the "coolthreads" hardware from Sun, in particular
> the T2000. This utilises the first generation "Niagra" chips which can handle
> up to 32 threads per socket.
>
> The technology looks pretty good apart from the fact that they only have a
> single FPU per socket.
>
> My question is, how much FP does a typical mail server (sendmail/MS/MW etc)
> need? Is it even worth going through the evaluation procedure or should I
> wait until the Niagra2 chips arrive (May apparently) which will have one FPU
> per core? Anyone here using this hardware?
We have two 8-core T2000s and three 8-core T1000s onsite. The three T1000s
handle our webmail front end (horde/imp and associated apache stuff).
One T2000 is a web server, and the second T2000 came online a couple of
weeks ago to handle our IMAP service (dovecot 1.0rc18 currently). This
box has an HP MSA50 disk array with fourteen 72GB disks in a mirrored/
striped ZFS disk pool for homedirs. All of these systems do a great job,
and barely break a sweat doing it.
While I can't speak to the FPU issue directly, I got a bit of advice from
a Sun engineer on which chipset to buy for what use in Sun-land. If you
want floating-point computation speed, buy x86 boxes (Sun V20's, etc) because
the clock cycle of the x86 chips is so much faster. If the work is non
floating-point, then buy Coolthreads servers if the ratio of threads to
processes is > 4. How to find out? Run "prstat" and look at the bottom
line. Take the ratio of processes to LWPs. If the ratio is less than
four, then buy standard Sparc. Sparc chips have the advantage that they
are RISC chips while x86 aren't. His advice, passed along.
Jeff Earickson
Colby College
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